# cvkbdcpld.ucf - Constraints reflecting XC9572XL PLCC44
#
# Some general I/O pins are special
#   LOC=P5,P6,P7 are GCK1,2,3
#   LOC=P42,P40 is GTS1,2
#   LOC=P39 is GSR
#

# General I/O pins
# Looking from above, these walk from 12 o'clock, backwards to 1 o'clock
# Optimised the layout to match the PCB
NET A<7>     LOC=P1  ;
NET A<6>     LOC=P2  ;
NET A<5>     LOC=P3  ;
NET A<4>     LOC=P4  ;
NET A<2>     LOC=P5  ;
NET D<4>     LOC=P6  ;
NET D<6>     LOC=P7  ;
NET D<7>     LOC=P8  ;
NET M1_n     LOC=P9  ;
NET D<0>     LOC=P11 ;
NET D<1>     LOC=P12 ;
NET WR_n     LOC=P13 ;
NET D<3>     LOC=P14 ;
NET IORQ_n   LOC=P18 ;
NET RD_n     LOC=P19 ;
NET D<5>     LOC=P20 ;
NET D<2>     LOC=P22 ;
NET A<3>     LOC=P24 ;
NET PS2_CLK5 LOC=P25 ;
NET PS2_DAT5 LOC=P26 ;
NET KC<2>    LOC=P27 ;
NET KC<1>    LOC=P28 ;
NET KC<0>    LOC=P29 ;
NET KD<6>    LOC=P33 ;
NET KD<7>    LOC=P34 ;
NET KD<0>    LOC=P35 ;
NET KD<1>    LOC=P36 ;
NET KD<2>    LOC=P37 ;
NET KD<3>    LOC=P38 ;
NET KD<4>    LOC=P39 ;
NET KD<5>    LOC=P40 ;
NET PS2_CLK  LOC=P42 ;
NET PS2_DAT  LOC=P43 ;
NET K_WR_n   LOC=P44 ;

# JTAG for programming
# NET tdi LOC=P15 ;
# NET tms LOC=P16 ;
# NET tck LOC=P17 ;
# NET tdo LOC=P30 ;

# Power and ground
# NET vcc1  LOC=P21 ;
# NET vcc2  LOC=P41 ;
# NET vccio LOC=P42 ;
# NET gnd1  LOC=P10 ;
# NET gnd2  LOC=P23 ;
# NET gnd3  LOC=P31 ;
