 
cpldfit:  version P.15xf                            Xilinx Inc.
                                  Fitter Report
Design Name: cvkbdcpld                           Date:  9-20-2013, 11:46AM
Device Used: XC9572XL-10-PC44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
14 /72  ( 19%) 25  /360  (  7%) 47 /216 ( 22%)   3  /72  (  4%) 34 /34  (100%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1           3/18       12/54        6/90       9/ 9*
FB2           3/18       10/54        3/90       9/ 9*
FB3           5/18       14/54       10/90       9/ 9*
FB4           3/18       11/54        6/90       7/ 7*
             -----       -----       -----      -----    
             14/72       47/216      25/360     34/34 

* - Resource is exhausted

** Global Control Resources **

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   20          20    |  I/O              :    28      28
Output        :   11          11    |  GCK/IO           :     3       3
Bidirectional :    3           3    |  GTS/IO           :     2       2
GCK           :    0           0    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     34          34

** Power Data **

There are 14 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'cvkbdcpld.ise'.
INFO:Cpld - Inferring BUFG constraint for signal 'A<2>' based upon the LOC
   constraint 'P5'. It is recommended that you declare this BUFG explicitedly in
   your design. Note that for certain device families the output of a BUFG
   constraint can not drive a gated clock, and the BUFG constraint will be
   ignored.
WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'A_2_IBUF' is
   ignored. Most likely the signal is gated and therefore cannot be used as a
   global control signal.
*************************  Summary of Mapped Logic  ************************

** 14 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
D<4>                2     10    FB1_11  6    GCK/I/O O       STD  FAST 
D<6>                2     10    FB1_14  7    GCK/I/O O       STD  FAST 
D<7>                2     10    FB1_15  8    I/O     O       STD  FAST 
PS2_CLK             1     1     FB2_14  42   GTS/I/O O       STD  FAST 
PS2_DAT             1     1     FB2_15  43   I/O     O       STD  FAST 
K_WR_n              1     8     FB2_17  44   I/O     O       STD  FAST 
D<0>                2     10    FB3_2   11   I/O     I/O     STD  FAST 
D<1>                2     10    FB3_5   12   I/O     I/O     STD  FAST 
D<3>                2     10    FB3_9   14   I/O     O       STD  FAST 
D<5>                2     10    FB3_15  20   I/O     O       STD  FAST 
D<2>                2     10    FB3_17  22   I/O     I/O     STD  FAST 
KC<2>               2     9     FB4_8   27   I/O     O       STD  FAST RESET
KC<1>               2     9     FB4_11  28   I/O     O       STD  FAST RESET
KC<0>               2     9     FB4_14  29   I/O     O       STD  FAST RESET

** 20 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
A<7>                FB1_2   1    I/O     I
A<6>                FB1_5   2    I/O     I
A<5>                FB1_6   3    I/O     I
A<4>                FB1_8   4    I/O     I
A<2>                FB1_9   5    GCK/I/O I
M1_n                FB1_17  9    I/O     I
KD<0>               FB2_2   35   I/O     I
KD<1>               FB2_5   36   I/O     I
KD<2>               FB2_6   37   I/O     I
KD<3>               FB2_8   38   I/O     I
KD<4>               FB2_9   39   GSR/I/O I
KD<5>               FB2_11  40   GTS/I/O I
WR_n                FB3_8   13   I/O     I
IORQ_n              FB3_11  18   I/O     I
RD_n                FB3_14  19   I/O     I
A<3>                FB3_16  24   I/O     I
PS2_CLK5            FB4_2   25   I/O     I
PS2_DAT5            FB4_5   26   I/O     I
KD<6>               FB4_15  33   I/O     I
KD<7>               FB4_17  34   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               12/42
Number of signals used by logic mapping into function block:  12
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1         (b)     
(unused)              0       0     0   5     FB1_2   1     I/O     I
(unused)              0       0     0   5     FB1_3         (b)     
(unused)              0       0     0   5     FB1_4         (b)     
(unused)              0       0     0   5     FB1_5   2     I/O     I
(unused)              0       0     0   5     FB1_6   3     I/O     I
(unused)              0       0     0   5     FB1_7         (b)     
(unused)              0       0     0   5     FB1_8   4     I/O     I
(unused)              0       0     0   5     FB1_9   5     GCK/I/O I
(unused)              0       0     0   5     FB1_10        (b)     
D<4>                  2       0     0   3     FB1_11  6     GCK/I/O O
(unused)              0       0     0   5     FB1_12        (b)     
(unused)              0       0     0   5     FB1_13        (b)     
D<6>                  2       0     0   3     FB1_14  7     GCK/I/O O
D<7>                  2       0     0   3     FB1_15  8     I/O     O
(unused)              0       0     0   5     FB1_16        (b)     
(unused)              0       0     0   5     FB1_17  9     I/O     I
(unused)              0       0     0   5     FB1_18        (b)     

Signals Used by Logic in Function Block
  1: A<2>               5: A<6>               9: KD<6> 
  2: A<3>               6: A<7>              10: KD<7> 
  3: A<4>               7: IORQ_n            11: M1_n 
  4: A<5>               8: KD<4>             12: RD_n 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
D<4>                 XXXXXXXX..XX............................ 10
D<6>                 XXXXXXX.X.XX............................ 10
D<7>                 XXXXXXX..XXX............................ 10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               10/44
Number of signals used by logic mapping into function block:  10
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1         (b)     
(unused)              0       0     0   5     FB2_2   35    I/O     I
(unused)              0       0     0   5     FB2_3         (b)     
(unused)              0       0     0   5     FB2_4         (b)     
(unused)              0       0     0   5     FB2_5   36    I/O     I
(unused)              0       0     0   5     FB2_6   37    I/O     I
(unused)              0       0     0   5     FB2_7         (b)     
(unused)              0       0     0   5     FB2_8   38    I/O     I
(unused)              0       0     0   5     FB2_9   39    GSR/I/O I
(unused)              0       0     0   5     FB2_10        (b)     
(unused)              0       0     0   5     FB2_11  40    GTS/I/O I
(unused)              0       0     0   5     FB2_12        (b)     
(unused)              0       0     0   5     FB2_13        (b)     
PS2_CLK               1       0     0   4     FB2_14  42    GTS/I/O O
PS2_DAT               1       0     0   4     FB2_15  43    I/O     O
(unused)              0       0     0   5     FB2_16        (b)     
K_WR_n                1       0     0   4     FB2_17  44    I/O     O
(unused)              0       0     0   5     FB2_18        (b)     

Signals Used by Logic in Function Block
  1: A<2>               5: A<6>               8: PS2_CLK5 
  2: A<3>               6: A<7>               9: PS2_DAT5 
  3: A<4>               7: IORQ_n            10: WR_n 
  4: A<5>             

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
PS2_CLK              .......X................................ 1
PS2_DAT              ........X............................... 1
K_WR_n               XXXXXXX..X.............................. 8
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               14/40
Number of signals used by logic mapping into function block:  14
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1         (b)     
D<0>                  2       0     0   3     FB3_2   11    I/O     I/O
(unused)              0       0     0   5     FB3_3         (b)     
(unused)              0       0     0   5     FB3_4         (b)     
D<1>                  2       0     0   3     FB3_5   12    I/O     I/O
(unused)              0       0     0   5     FB3_6         (b)     
(unused)              0       0     0   5     FB3_7         (b)     
(unused)              0       0     0   5     FB3_8   13    I/O     I
D<3>                  2       0     0   3     FB3_9   14    I/O     O
(unused)              0       0     0   5     FB3_10        (b)     
(unused)              0       0     0   5     FB3_11  18    I/O     I
(unused)              0       0     0   5     FB3_12        (b)     
(unused)              0       0     0   5     FB3_13        (b)     
(unused)              0       0     0   5     FB3_14  19    I/O     I
D<5>                  2       0     0   3     FB3_15  20    I/O     O
(unused)              0       0     0   5     FB3_16  24    I/O     I
D<2>                  2       0     0   3     FB3_17  22    I/O     I/O
(unused)              0       0     0   5     FB3_18        (b)     

Signals Used by Logic in Function Block
  1: A<2>               6: A<7>              11: KD<3> 
  2: A<3>               7: IORQ_n            12: KD<5> 
  3: A<4>               8: KD<0>             13: M1_n 
  4: A<5>               9: KD<1>             14: RD_n 
  5: A<6>              10: KD<2>            

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
D<0>                 XXXXXXXX....XX.......................... 10
D<1>                 XXXXXXX.X...XX.......................... 10
D<3>                 XXXXXXX...X.XX.......................... 10
D<5>                 XXXXXXX....XXX.......................... 10
D<2>                 XXXXXXX..X..XX.......................... 10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               11/43
Number of signals used by logic mapping into function block:  11
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
(unused)              0       0     0   5     FB4_2   25    I/O     I
(unused)              0       0     0   5     FB4_3         (b)     
(unused)              0       0     0   5     FB4_4         (b)     
(unused)              0       0     0   5     FB4_5   26    I/O     I
(unused)              0       0     0   5     FB4_6         (b)     
(unused)              0       0     0   5     FB4_7         (b)     
KC<2>                 2       0     0   3     FB4_8   27    I/O     O
(unused)              0       0     0   5     FB4_9         (b)     
(unused)              0       0     0   5     FB4_10        (b)     
KC<1>                 2       0     0   3     FB4_11  28    I/O     O
(unused)              0       0     0   5     FB4_12        (b)     
(unused)              0       0     0   5     FB4_13        (b)     
KC<0>                 2       0     0   3     FB4_14  29    I/O     O
(unused)              0       0     0   5     FB4_15  33    I/O     I
(unused)              0       0     0   5     FB4_16        (b)     
(unused)              0       0     0   5     FB4_17  34    I/O     I
(unused)              0       0     0   5     FB4_18        (b)     

Signals Used by Logic in Function Block
  1: A<2>               5: A<6>               9: D<1>.PIN 
  2: A<3>               6: A<7>              10: D<2>.PIN 
  3: A<4>               7: IORQ_n            11: WR_n 
  4: A<5>               8: D<0>.PIN         

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
KC<2>                XXXXXXX..XX............................. 9
KC<1>                XXXXXXX.X.X............................. 9
KC<0>                XXXXXXXX..X............................. 9
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


D_I(0) <= KD(0);
D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
D_OE(0) <= (M1_n AND NOT RD_n AND NOT IORQ_n AND NOT A(3) AND NOT A(2) AND A(4) AND 
	NOT A(7) AND NOT A(6) AND A(5));


D_I(1) <= KD(1);
D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
D_OE(1) <= (M1_n AND NOT RD_n AND NOT IORQ_n AND NOT A(3) AND NOT A(2) AND A(4) AND 
	NOT A(7) AND NOT A(6) AND A(5));


D_I(2) <= KD(2);
D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
D_OE(2) <= (M1_n AND NOT RD_n AND NOT IORQ_n AND NOT A(3) AND NOT A(2) AND A(4) AND 
	NOT A(7) AND NOT A(6) AND A(5));


D_I(3) <= KD(3);
D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
D_OE(3) <= (M1_n AND NOT RD_n AND NOT IORQ_n AND NOT A(3) AND NOT A(2) AND A(4) AND 
	NOT A(7) AND NOT A(6) AND A(5));


D_I(4) <= KD(4);
D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
D_OE(4) <= (M1_n AND NOT RD_n AND NOT IORQ_n AND NOT A(3) AND NOT A(2) AND A(4) AND 
	NOT A(7) AND NOT A(6) AND A(5));


D_I(5) <= KD(5);
D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
D_OE(5) <= (M1_n AND NOT RD_n AND NOT IORQ_n AND NOT A(3) AND NOT A(2) AND A(4) AND 
	NOT A(7) AND NOT A(6) AND A(5));


D_I(6) <= KD(6);
D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
D_OE(6) <= (M1_n AND NOT RD_n AND NOT IORQ_n AND NOT A(3) AND NOT A(2) AND A(4) AND 
	NOT A(7) AND NOT A(6) AND A(5));


D_I(7) <= KD(7);
D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
D_OE(7) <= (M1_n AND NOT RD_n AND NOT IORQ_n AND NOT A(3) AND NOT A(2) AND A(4) AND 
	NOT A(7) AND NOT A(6) AND A(5));

FDCPE_KC0: FDCPE port map (KC(0),D(0).PIN,KC_C(0),'0','0');
KC_C(0) <= NOT ((NOT IORQ_n AND NOT WR_n AND NOT A(3) AND NOT A(2) AND A(4) AND NOT A(7) AND 
	NOT A(6) AND A(5)));

FDCPE_KC1: FDCPE port map (KC(1),D(1).PIN,KC_C(1),'0','0');
KC_C(1) <= NOT ((NOT IORQ_n AND NOT WR_n AND NOT A(3) AND NOT A(2) AND A(4) AND NOT A(7) AND 
	NOT A(6) AND A(5)));

FDCPE_KC2: FDCPE port map (KC(2),D(2).PIN,KC_C(2),'0','0');
KC_C(2) <= NOT ((NOT IORQ_n AND NOT WR_n AND NOT A(3) AND NOT A(2) AND A(4) AND NOT A(7) AND 
	NOT A(6) AND A(5)));


K_WR_n <= NOT ((NOT IORQ_n AND NOT WR_n AND NOT A(3) AND NOT A(2) AND A(4) AND NOT A(7) AND 
	NOT A(6) AND A(5)));


PS2_CLK <= PS2_CLK5;


PS2_DAT <= PS2_DAT5;

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572XL-10-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11       XC9572XL-10-PC44     35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 A<7>                             23 GND                           
  2 A<6>                             24 A<3>                          
  3 A<5>                             25 PS2_CLK5                      
  4 A<4>                             26 PS2_DAT5                      
  5 A<2>                             27 KC<2>                         
  6 D<4>                             28 KC<1>                         
  7 D<6>                             29 KC<0>                         
  8 D<7>                             30 TDO                           
  9 M1_n                             31 GND                           
 10 GND                              32 VCC                           
 11 D<0>                             33 KD<6>                         
 12 D<1>                             34 KD<7>                         
 13 WR_n                             35 KD<0>                         
 14 D<3>                             36 KD<1>                         
 15 TDI                              37 KD<2>                         
 16 TMS                              38 KD<3>                         
 17 TCK                              39 KD<4>                         
 18 IORQ_n                           40 KD<5>                         
 19 RD_n                             41 VCC                           
 20 D<5>                             42 PS2_CLK                       
 21 VCC                              43 PS2_DAT                       
 22 D<2>                             44 K_WR_n                        


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572xl-10-PC44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25
