Release 14.1 - xst P.15xf (lin)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
--> 
Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
 
--> 
Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
 
--> 
Reading design: cvkbdcpld.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "cvkbdcpld.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "cvkbdcpld"
Output Format                      : NGC
Target Device                      : XC9500XL CPLDs

---- Source Options
Top Module Name                    : cvkbdcpld
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
Mux Extraction                     : Yes
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : Yes
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Verilog 2001                       : YES

---- Other Options
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "/work/ak/cv/cvkbd/ise/vhdl/cvkbdcpld.vhd" in Library work.
Entity <cvkbdcpld> compiled.
Entity <cvkbdcpld> (Architecture <behavior>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <cvkbdcpld> in library <work> (architecture <behavior>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <cvkbdcpld> in library <work> (Architecture <behavior>).
Entity <cvkbdcpld> analyzed. Unit <cvkbdcpld> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <cvkbdcpld>.
    Related source file is "/work/ak/cv/cvkbd/ise/vhdl/cvkbdcpld.vhd".
    Found 8-bit tristate buffer for signal <$mux0000>.
    Found 3-bit register for signal <KC_int>.
    Summary:
	inferred   8 Tristate(s).
Unit <cvkbdcpld> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                                            : 1
 3-bit register                                        : 1
# Tristates                                            : 1
 8-bit tristate buffer                                 : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <cvkbdcpld> ...
  implementation constraint: INIT=r	 : KC_int_2
  implementation constraint: INIT=r	 : KC_int_0
  implementation constraint: INIT=r	 : KC_int_1

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : cvkbdcpld.ngr
Top Level Output File Name         : cvkbdcpld
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : Yes
Target Technology                  : XC9500XL CPLDs
Macro Preserve                     : YES
XOR Preserve                       : YES
Clock Enable                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 34

Cell Usage :
# BELS                             : 12
#      AND4                        : 1
#      INV                         : 5
#      OR2                         : 5
#      OR3                         : 1
# FlipFlops/Latches                : 3
#      FD                          : 3
# IO Buffers                       : 34
#      IBUF                        : 20
#      IOBUFE                      : 3
#      OBUF                        : 6
#      OBUFE                       : 5
=========================================================================


Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 4.87 secs
 
--> 


Total memory usage is 160544 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

